Recently as the degree of integration of semiconductor devices increases, the power consumption of semiconductor devices is also increasing. Therefore power saving of semiconductor devices is demanded, and an example of circuits, for which power consumption is suppressed, is a circuit disclosed in Japanese Patent Application Laid-Open No. 2000-232339. However the technology disclosed in Japanese Patent Application Laid-Open No. 2000-232339 concerns the power saving of a flip-flop circuit, and cannot be applied to dynamic circuits in general.
Out of CMOS circuits of which power can be saved, a static circuit is constructed by a combination of n-type MOS transistors and p-type MOS transistors according to the number of inputs. However the operation speed of a p-type MOS transistor is slower than that of an n-type MOS transistor, and it is desirable that the p-type MOS transistors are not connected in series as much as possible in order to increase the speed of the circuit.
FIG. 1 is a diagram depicting an 8-input OR circuit implemented by static circuits. The 8-input terminals a0-a7 of the OR circuit in FIG. 1 are connected to the gates of the 8 p-type MOS transistors 410-417 and the 8 n-type MOS transistors 420-427 respectively. An inverter 430 is connected to a node 440 of the p-type MOS transistors 410-417 connected in series and the n-type MOS transistors 420-427 connected in parallel, and the output of [the inverter 430] becomes the output terminal of this OR circuit.
In this OR circuit, if all 8-inputs a0-a7 become low level (hereafter L level), all the p-type MOS transistors 410-417 turn ON, and the node 440 becomes high level (hereafter H level). And the L level, inverted by the inverter 430, is output to the output z. In this case, the delay time is long since all 8 p-type MOS transistors 417-410 must turn ON. In this way, if an OR circuit having a large number of inputs, as above, is constructed by a static circuit, the operation speed drops since the p-type MOS transistors are connected in series, and this causes a drop in the operation speed of the entire device. In order to decrease the number of p-type MOS transistors connected in series, the number of logical stages must be increased, so the delay time per stage is improved, but the total delay time improves little.
Because of this, a dynamic circuit was proposed in order to improve the delay in operation due to the p-type MOS transistors. Now for simplification a dynamic circuit will be described using the case of an 8-input OR circuit as an example.
FIG. 2 is a block diagram depicting an 8-input OR circuit implemented by a dynamic circuit. Between a p-type MOS transistor 520, to which clock CK is input, and an n-type MOS transistor 550, 8 n-type MOS transistors 510-517 are connected in parallel. The input terminals b0-b7 of the 8-input OR circuit are connected respectively to the gates of the n-type MOS transistors 510-517. An inverter 540 is connected to a node 560 between the p-type MOS transistor 520 and the 8 n-type type transistors 510-517 connected in parallel, and the output thereof becomes the output of the 8-input OR circuit. A p-type MOS transistor 530 is provided for latching the H level of the node 560, and the output of the inverter 540 is also input to this gate.
In this circuit, if the clock CK becomes L level, the p-type MOS transistor 520 is turned ON, the n-type MOS transistor 550 is turned OFF, the node 560 is precharged, and the output z in this case becomes L level, regardless the values of the input a0-a7 (precharge mode). And when the clock CK becomes H level, the n-type MOS transistor 550 is turned ON, and the computing result is output (evaluation mode). If all of the 8-inputs b0-b7 are L level, the output z is L level since the node 560 remains precharged by the p-type MOS transistor 530. In this case, the output z, which was reset to L level when the clock CL is in L level, remains L level even after the clock CK is switched to H level. In other words, the delay time in this case is 0. If one of the 8-inputs b0-b7 is H level, on the other hand, the output z becomes H level since the node 560 is discharged when the H level is input to the clock CK. The delay time in this case [is generated] only for one inverter on the path from the ground to the output terminal and 2 n-type MOS transistors.
In this way, if a dynamic circuit is used, the delay time can be decreased compared with the case of using a static circuit.